AS1123
Datasheet - D e t a i l e d D e s c r i p t i o n
Serial Interface
Data accesses are made serially via pins SDI and SDO. At each CLK rising edge, the signal present at pin SDI is shifted into the first bit of the
internal shift register and the other bits are shifted ahead of the first bit. The MSB is the first bit to be clocked in. In error-detection mode the shift
register will latch-in the corresponding error data of temperature-, open-, and short-error register with each falling edge of LD.
The 16-bit data register will latch the data of the shift register at each rising edge of LD. This data is then used to drive the current generator out-
put drivers to switch on the corresponding LEDs as OEN goes low.
Timing Diagrams
This section contains timing diagrams referenced in other sections of this data sheet.
Figure 9. Normal Mode Timing Diagram
t W(CLK)
CLK
SDI
SDO
50%
50%
t SU(D)
t H(D)
50%
50%
50%
50%
t P1
t W(L)
LD
OEN
t SU(L)
50%
50%
t H(L)
OEN Low = Output Enabled
OUTN x
Figure 10. Output Delay Timing Diagram
t P2
50%
OUTN x High = Output Off
OUTN x Low = Output On
OEN
50%
t P3
t W(OE)
50%
t P3
OUTN0:15
90%
90%
50%
t OF
10%
10%
t OR
50%
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